Data transfer control system, electronic instrument, and data transfer control method

ABSTRACT

A data transfer control system receives a command packet ORB transferred through a bus BUS  1  (IEEE 1394), issues a command indicated by ORB to a device connected to a bus BUS 2  (ATA (IDE)/ATAPI), and orders start of a DMA transfer. The command issued based on ORB is aborted after the completion of the DMA transfer. The data transfer control system compares contents of a command packet ORB 1  transferred before a bus reset with contents of a command packet ORB 2  transferred after the bus reset. If the contents are different, a command issued based on ORB 1  is aborted after completion of a DMA transfer. Dummy data is transferred between the data transfer control system and the device connected to the bus BUS 2  until a DMA transfer is completed. Dummy data transfer is controlled by performing a dummy update on a pointer.

[0001] Japanese Patent Application No. 2002-227303 filed on Aug. 5,2002, is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a data transfer control system,an electronic instrument, a program, and a data transfer control method.

[0003] In recent years, an interface standard called IEEE 1394 hasattracted attention. Not only can computer peripherals such as hard diskdrives, optical disk drives, printers, and scanners be connected to abus under this IEEE 1394, but also domestic electrical products such asvideo cameras, VCRs, and TVs. That is why this standard is expected toenable a dramatic acceleration in the digitalization of electronicinstruments.

[0004] In the IEEE 1394, when the number of nodes connected to a bus ischanged, such as when an additional electronic instrument is connectedto the bus or when an electronic instrument is removed from the bus, abus reset occurs. If a bus reset occurs, node topology information iscleared. The node topology information is automatically recreated afterthe bus reset.

[0005] In IEEE 1394, since the node topology information isautomatically recreated after the bus reset, a so-called hot plug isenabled. That is, a user can plug and unplug electronic instruments atany time in the same manner as in conventional domestic electricalappliances such as VCRs. This contributes to popularization of a homenetwork system.

[0006] However, various problems may be caused by the bus reset. When acommand is issued to a hard disc drive (or a storage device in a broadsense, or a device in a broader sense) and a direct memory access (DMA)transfer is initiated, if a bus reset occurs during the DMA transfer,the hard disc drive may hang up, for example.

[0007] As conventional technique for solving various problems caused bythe occurrence of the bus reset, a technique disclosed in JapanesePatent Application Laid-open No. 2001-177537 is known, for example.

BRIEF SUMMARY OF THE INVENTION

[0008] According to one aspect of the present invention, there isprovided a data transfer control system for data transfer through a bus,comprising:

[0009] a command processing section which receives a command packettransferred through a first bus, issues a command indicated by thecommand packet to a device connected to a second bus, and orders startof a direct memory access (DMA) transfer through the second bus; and

[0010] a command abort section which aborts the command issued to thedevice connected to the second bus based on the command packet after thecompletion of the DMA transfer started based on the command packet.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0011]FIG. 1 is a diagram illustrative of a layer structure of IEEE 1394and Serial Bus Protocal 2 (SBP-2).

[0012]FIG. 2 is a diagram illustrative of a summary of processing ofSBP-2.

[0013]FIG. 3 is a diagram illustrative of command processing in the caseof transferring data from an initiator to a target in SBP-2.

[0014]FIG. 4 is a diagram illustrative of command processing in the caseof transferring data from a target to an initiator in SBP-2.

[0015]FIGS. 5A to 5C are diagrams for describing a page table.

[0016]FIG. 6 is a diagram illustrative of node topology informationwhich is cleared by a bus reset.

[0017]FIGS. 7A and 7B are diagrams for describing a problem which occurswhen a bus reset occurs during data transfer.

[0018]FIG. 8 is a diagram showing a configurational example of a datatransfer control system and an electronic instrument in one embodimentof the present invention.

[0019]FIG. 9 is a flowchart showing a detailed processing according toone embodiment of the present invention.

[0020]FIG. 10 is a flowchart showing a detailed processing according toone embodiment of the present invention.

[0021]FIG. 11 is a diagram illustrative of resume processing of datatransfer.

[0022]FIG. 12 is a diagram illustrative of comparison of contents ofORBs.

[0023]FIG. 13 is a diagram illustrative of command abort processing.

[0024]FIGS. 14A to 14E are diagrams for describing pointer control (inreading) for implementing processing of dummy data transfer.

[0025]FIGS. 15A to 15E are diagrams for describing pointer control (inwriting) for implementing processing of dummy data transfer.

[0026]FIG. 16 is a diagram showing a configurational example of anATA/ATAPI interface circuit.

[0027]FIGS. 17A and 17B are waveform charts showing signal waveformexamples during PIO reading and PIO writing.

[0028]FIGS. 18A and 18B are waveform charts showing signal waveformexamples during DMA reading and DMA writing.

[0029]FIGS. 19A and 19B are waveform charts showing signal waveformexamples during UltraDMA reading and UltraDMA writing.

DETAILED DESCRIPTION OF THE EMBODIMENT

[0030] Embodiments of the present invention are described below.

[0031] Note that the embodiments described below do not in any way limitthe scope of the invention laid out in the claims herein. In addition,all elements of the embodiments described below should not be taken asessential requirements of the present invention.

[0032] 1. IEEE 1394 and SBP-2

[0033] 1.1 Layer Structure

[0034] A protocol called Serial Bus Protocol 2 (SBP-2) has been proposedas a higher level protocol including a part of a function of atransaction layer of IEEE 1394. SBP-2 (SBP in a broad sense) has beenproposed to enable a command set of SCSI (MMC-2) to be utilized on theprotocol of IEEE 1394. SBP-2 enables a command set which has been usedin an electronic instrument conforming to the SCSI standard to be usedin an electronic instrument conforming to the IEEE 1394 standard bymerely adding minimum changes to the command set. Therefore, the designand development of an electronic instrument can be facilitated.

[0035]FIG. 1 schematically shows a layer structure (or a protocol stack)of IEEE 1394 and SBP-2.

[0036] The protocols of IEEE 1394 (IEEE 1394-1995, P1394a, P1394b, etc.)include a transaction layer, a link layer, and a physical layer.

[0037] The transaction layer provides an upper layer with an interface(service) in a transaction unit, and performs transactions such as aread transaction, write transaction, and lock transaction through aninterface provided by the link layer in a lower layer.

[0038] In the read transaction, data is transferred to a requester nodefrom a responder node. In the write transaction, data is transferred tothe responder node from the requester node. In the lock transaction,data is transferred to the responder node from the requester node, andthe responder node processes the data and returns the processed data tothe requester node.

[0039] The link layer provides addressing, data checking, data framingfor packet transmission and reception, cycle control for isochronoustransfer, and the like.

[0040] The physical layer translates logical symbols used by the linklayer into electrical signals, arbitrates for the bus, and provides aphysical bus interface.

[0041] As shown in FIG. 1, an SBP-2 layer provides a higher levelprotocol including a part of the function of the transaction layer ofIEEE 1394 (first interface standard in a broad sense).

[0042] 1.2 Processing of SBP-2

[0043]FIG. 2 shows a flowchart of the entire processing of SBP-2 (firsthigher level protocol of the first interface standard in a broad sense).

[0044] In SBP-2, read processing of a configuration ROM is performed forconfirming connected devices as shown in FIG. 2 (step T1).

[0045] Login processing for allowing an initiator (personal computer,for example) to acquire an access right to a target (storage device, forexample) (request initiation permission; right to use the bus) isperformed (step T2). In more detail, the login processing is performedby using a login operation request block (ORB) created by the initiator.

[0046] A fetch agent is initialized (step T3). Command processing isperformed by using a command block ORB (normal command ORB) (step T4),and logout processing is performed by using a logout ORB. (step T5).

[0047] In the command processing in the step T4, the initiator transfersa write request packet (issues a write request transaction) to ring adoorbell register of the target, as indicated by A1 in FIG. 3. Thetarget transfers a read request packet, and the initiator returns a readresponse packet corresponding to the read request packet, as indicatedby A2. This allows the ORB (command block ORB) created by the initiatorto be fetched in a data-buffer (packet buffer) of the target. The targetanalyzes a command included in the ORB fetched in the data buffer.

[0048] If the command included in the ORB is a SCSI write command, thetarget transfers a read request packet to the initiator, and theinitiator returns a read response packet corresponding to the readrequest packet, as indicated by A3. This allows data stored in a databuffer of the initiator to be transferred to the target. In the casewhere the target is a storage device, the transferred data is written inthe storage device.

[0049] If the command included in the ORB is a SCSI read command, thetarget transfers a series of write request packets to the initiator, asindicated by B1 in FIG. 4. In the case where the target is a storagedevice, data read from the storage device is transferred to the databuffer of the initiator.

[0050] According to SBP-2, the target can transmit or receive data bytransferring a request packet (issuing a transaction) at itsconvenience. Therefore, since it is unnecessary for the initiator andthe target to operate in synchronization, data transfer efficiency canbe increased.

[0051] As a higher level protocol of IEEE 1394, an AV/C command which issuitable for transferring image and sound data has been proposed inaddition to SBP-2 which is suitable for transferring data of a storagedevice or a printer. As a protocol for transferring internet protocol(IP) packets on the IEEE 1394 bus, a protocol called IPover1394 has alsobeen proposed.

[0052] In the case of transferring data between the target and theinitiator, there may be a case where a page table is present in the databuffer of the initiator (personal computer or partner node) as shown inFIG. 5A, and a case where a page table is not present in the data bufferof the initiator.

[0053] In the case where a page table is present, the page table addressand the number of elements are included in an ORB created by theinitiator, as shown in FIG. 5B. The address (read address or writeaddress) of data to be transferred is indirectly addressed by using thepage table.

[0054] In the case where a page table is not present, an address anddata length are included in the ORB and data to be transferred isdirectly addressed, as shown in FIG. 5C.

[0055] 1.3 Bus Reset

[0056] In IEEE 1394, a bus reset occurs (is issued) when power to adevice is turned on or a device is plugged in or unplugged in the middleof a transaction. Specifically, each node monitors a change in voltageof the port. If the voltage of the port is changed due to connection ofa new node with the bus or the like, a node which detects the voltagechange notifies other nodes on the bus of occurrence of the bus reset.The physical layer of each node notifies the link layer of occurrence ofthe bus reset.

[0057] If the bus reset occurs, topology information (node ID and thelike) shown in FIG. 6 is cleared. The topology information is thenautomatically recreated. Specifically, tree identify and self-identifyprocesses are performed after the bus reset. Management nodes such as anisochronous resource manager, a cycle master, and a bus manager are thendetermined, and normal packet transfer is resumed.

[0058] In IEEE 1394, since the topology information is automaticallyrecreated after the bus reset, a cable can be plugged into or unpluggedfrom an electronic instrument at any time, whereby a so-called hot plugcan be implemented.

[0059] In the case where the bus reset occurs in the middle of atransaction, the transaction is canceled. The requester node which hasissued the canceled transaction retransfers the request packet after thetopology information is recreated. The responder node must not returnthe response packet of the transaction canceled by the bus reset to therequester node.

[0060] 1.4 Hang-up Due to Bus Reset

[0061] It was found that the following problem occurs if the bus resetoccurs during data transfer.

[0062] As shown in FIG. 7A, the bus reset occurs after data at alocation (address) indicated by C1 is transferred, for example. In thiscase, all transactions which are being processed when the bus resetoccurs are canceled. Therefore, the initiator such as a personalcomputer which has requested data transfer by using an ORB transferredbefore the bus reset (hereinafter may be called “ORB1”) recreates an ORBtransferred after the bus reset (hereinafter may be called “ORB2”), andorders the target such as a storage device to retransfer data, as shownin FIG. 7B. Therefore, data transfer is resumed at a location indicatedby C2 in FIG. 7B, whereby data is transferred twice.

[0063] In order to solve this problem, the technology disclosed inJapanese Patent Application Laid-open No. 2001-177537 employs a methodof comparing the contents of the ORB1 before the bus reset with thecontents of the ORB2 after the bus reset, and resuming data transfer ata location indicated by C3 in FIG. 7B if the contents of the ORB1 arethe same as the contents of the ORB2.

[0064] However, depending on the architecture of the operating system(OS) of the personal computer, an ORB2 having contents differing fromthe contents of the ORB1 before the bus reset may be transferred fromthe personal computer after the bus reset.

[0065] For example, the ORB1 contains the SCSI (MMC-2) write command asshown in FIG. 3, and the bus reset occurs during data transfer based onthe write command. In this case, the OS of the personal computer maysend an ORB2 containing a read command for a file allocation table (FAT)after the bus reset in order to check the contents of the FAT.

[0066] In this case, since the data write command is indicated by theORB1 before the bus reset and the FAT read command is indicated by theORB2 after the bus reset, the contents of the ORB1 differ from thecontents of the ORB2. Therefore, the write command of the ORB1 which hasbeen issued to the storage device in the subsequent stage must beaborted.

[0067] However, in the case where the DMA transfer has already beenstarted (or initiated) based on the write command of the ORB1 before thebus reset, a problem in which the storage device in the subsequent stagehangs occurs if the write command is aborted.

[0068] 2. Entire Configuration

[0069]FIG. 8 shows an entire configuration example of a data transfercontrol system capable of solving the above problem and an electronicinstrument including the data transfer control system. The followingdescription is given taking a case where a target which performs datatransfer between the initiator and the target is a storage device (harddisk drive, CD drive, DVD drive, or the like) as an example. However,the present invention is not limited thereto.

[0070] A personal computer (host computer) 2 including a data buffer 4is connected to an electronic instrument 8 through a bus BUS1 (firstbus) conforming to IEEE 1394. The electronic instrument 8 includes adata transfer control system 10 and a storage device 100 (device in abroad sense).

[0071] The electronic instrument 8 may include a system CPU, a systemmemory (ROM and RAM), an operating section, a signal processing device,and the like (not shown).

[0072] The data transfer control system 10 includes a physical layer(PHY) circuit 14, a link layer circuit 20, an SBP-2 circuit 22, aninterface circuit 30, a packet management circuit 38, and a packetbuffer 40 (data buffer). The data transfer control system 10 includes aCPU 42 and a flash memory 44 (EEPROM). The data transfer control system10 includes firmware 50 of which processing modules (program) are storedin the flash memory 44 and which is executed by the CPU 42 (processor ina broad sense). The data transfer control system 10 in this embodimentdoes not necessarily include all the circuit blocks and functionalblocks shown in FIG. 8. Some of the circuit blocks and functional blocksmay be omitted.

[0073] The physical layer circuit 14 is a circuit for implementing theprotocol of the physical layer shown in FIG. 1 by the hardware. Thephysical layer circuit 14 has a function of translating logical symbolsused by the link layer circuit 20 into electrical signals.

[0074] The link (& transaction) layer circuit 20 is a circuit forimplementing a part of the protocols of the link layer and thetransaction layer shown in FIG. 1 by the hardware. The link layercircuit 20 provides various services for packet transfer between thenodes.

[0075] Data transfer conforming to IEEE 1394 can be performed betweenthe electronic instruments and the personal computer 2 (an electronicinstrument in a broad sense) through the bus BUS1 (first bus) byutilizing the functions of the physical layer circuit 14 and the linklayer circuit 20.

[0076] The SBP-2 circuit 22 (transfer execution circuit) is a circuitwhich implements a part of the SBP-2 protocol and a part of thetransaction layer by the hardware. Processing for dividing transfer datainto a series of packets and continuously transferring the dividedseries of packets can be implemented by the function of the SBP-2circuit 22.

[0077] The interface circuit 30 is a circuit which performs interfaceprocessing between the data transfer control system 10 and the storagedevice 100. Data transfer conforming to AT Attachment (ATA) and ATAPacket Interface (ATAPI) can be performed between the data transfercontrol system 10 and the storage device 100 through a bus BUS2 (secondbus) by the function of the interface circuit 30.

[0078] The data transfer control system 10 can be provided with aconversion bridge function between IEEE 1394 (first interface standardin a broad sense) and ATA (IDE)/ATAPI (second interface standard in abroad sense) by providing the physical layer circuit 14, the link layercircuit 20, and the interface circuit 30 as shown in FIG. 8.

[0079] A DMA controller 32 included in the interface circuit 30 is acircuit for performing direct memory access (DMA) transfer between thedata transfer control system 10 and the storage device 100 through thebus BUS2.

[0080] The storage device 100 connected to the bus BUS2 includes aninterface circuit 102 for performing data transfer conforming to ATA(IDE)/ATAPI, and an access control circuit 104 which controls access(write or read) to a storage 106 such as a hard disk or optical disk.

[0081] The buffer management circuit 38 is a circuit which manages aninterface between the packet buffer 40 and the link layer circuit 20 andthe like. The buffer management circuit 38 includes registers forcontrolling the buffer management circuit 38, an arbitration circuitwhich arbitrates for bus connection to the packet buffer 40, a sequencerwhich generates various control signals, and the like.

[0082] The buffer management circuit 38 includes a pointer managementsection 39. The pointer management section 39 manages pointers of thepacket buffer 40 by using a ring buffer, and updates a plurality ofpointers for writing and reading.

[0083] The packet buffer 40 (packet memory or data buffer) is a bufferfor temporarily storing packets (transferred data), and is formed byhardware such as an SRAM, SDRAM, or DRAM. In this embodiment, the packetbuffer 40 functions as a randomly accessible packet storage section. Thepacket buffer 40 may not be included in the data transfer control system10 and be provided externally.

[0084] The CPU 42 (processor in a broad sense) controls the entiredevice and data transfer.

[0085] The flash memory 44 (EEPROM) is an electrically erasableprogrammable nonvolatile memory. The processing modules (program) of thefirmware 50 are stored in the flash memory 44.

[0086] The firmware 50 is a program which includes various processingmodules (processing routines) and operates on the CPU 42. The protocolsof the transaction layer and the like are implemented by the firmware 50and the hardware such as the CPU 42.

[0087] The firmware 50 (F/W) includes a communication section 52, amanagement section 60, a fetch section 70, a storage task section 80,and a downloader 90. The firmware 50 does not necessarily include all ofthese functional blocks. Some of the functional blocks may be omitted.

[0088] The communication section 52 is a processing module whichfunctions as an interface between the firmware 50 and the hardware suchas the physical layer circuit 14 and the link layer circuit 20.

[0089] The management section 60 (management agent) is a processingmodule which manages a login, reconnect, logout, reset, and the like. Inthe case where the initiator requests a login to the target, themanagement section 60 receives the login request.

[0090] The fetch section 70 (fetch agent) is a processing module whichreceives an operation request block (ORB), issues a command status, andrequests the storage task section 80 to perform command processing. Thefetch section 70 can also handle a link list of an ORB fetched by thefetch section 70 in response to the request from the initiator,differing from the management section 60 which can handle only a singlerequest.

[0091] The storage task section 80 is a processing module for processinga command included in an ORB and processing DMA transfer.

[0092] The downloader 90 is a processing module for updating theprocessing module of the firmware 50 stored in the flash memory 44 andthe like.

[0093] The storage task section 80 includes a command processing section82, a command comparison section 84, a command abort section 86, and atransfer resume section 88.

[0094] The command processing section 82 performs various types ofprocessing of an ORB (command packet or a command packet for datatransfer operation request in a broad sense) transferred through the busBUS 1 (first bus conforming to the first interface standard such as IEEE1394). In more detail, the command processing section 82 receives an ORBfrom the bus BUS1, issues a command (SCSI or MMC-2 command) included inthe ORB to the storage device 100 (device in a broad sense) connected tothe bus BUS2 (second bus of the second interface standard such asATA/ATAPI), and orders start of DMA transfer (data transfer withoutinvolving the CPU) through the bus BUS2.

[0095] If the bus reset (reset which clears node topology information)occurs during processing of an ORB (during data transfer based on theORB), the command comparison section 84 compares the contents of theORB1 transferred through the bus BUS1 before the bus reset with thecontents of an ORB2 transferred through the bus BUS1 after the busreset.

[0096] The command abort section 86 aborts the command (SCSI readcommand, SCSI write command, or the like) which has been issued to thestorage device 100 based on the ORB after completion of the DMA transfer(continuous data transfer) started based on the ORB (command).

[0097] In more detail, if the contents of the ORB1 before the bus resetare determined to differ from the contents of the ORB2 after the busreset, the command abort section 86 aborts (terminates or cancels) thecommand which has been issued to the storage device 100 based on theORB1 after completion of the DMA transfer initiated based on the ORB1(command).

[0098] In this case, the command abort section 86 controls so that dummydata is transferred between the data transfer control system 10 and thestorage device 100 until the DMA transfer started based on the ORB iscompleted.

[0099] In the data transfer control system 10 in this embodiment havinga bus conversion bridge function, data transferred from the storagedevice 100 through the bus BUS2 is transferred to the personal computer2 through the bus BUS1. Data transferred from the personal computer 2through the bus BUS1 is transferred to the storage device 100 throughthe bus BUS2.

[0100] In the dummy data transfer, dummy data is transferred to the datatransfer control system 10 from the storage device 100 through the busBUS2, but is not transferred to the personal computer 2. Dummy data istransferred to the storage device 100 through the bus BUS2 even if datais not transferred to the data transfer control system 10 from thepersonal computer 2 through the bus BUS1.

[0101] The command abort section 86 performs the abort processing afterreconnect processing performed after the bus reset is completed.

[0102] The transfer resume section 88 performs processing for resumingdata transfer where the bus reset occurred (data subsequent to the datatransferred when the bus reset occurred) if the contents of the ORB1before the bus reset are determined to be the same as the contents ofthe ORB2 after the bus reset.

[0103] 3. Details of Processing

[0104] Details of processing in this embodiment are described belowusing flowcharts shown in FIGS. 9 and 10 and the like.

[0105]FIG. 9 is a flowchart showing overall processing in thisembodiment.

[0106] If the data transfer control system 10 receives an ORB1 includinga command CMD1 during SBP-2 processing (step S1), the data transfercontrol system 10 judges whether or not the bus reset has occurred (stepS2). If the bus reset has not occurred, the data transfer control system10 issues the command CMD1 included in the ORB1 to the storage device100 (hard disk drive) as indicated by D1 in FIG. 11 (step S3).

[0107] Specifically, since commands similar to those of SCSI (MMC-2)(read, write, mode sense, mode select, and the like) are used in SBP-2,the storage device 100 performs operations such as reading or writing byusing these commands. The data transfer control system 10 in thisembodiment retrieves the command CMD1 included in the ORB1, and issuesthe command CMD1 to the storage device 100 through the interface circuit30 and the bus BUS2 (ATA/ATAPI).

[0108] After issuing the command CMD1, the data transfer control system10 judges whether or not the bus reset has occurred (step S4). If thebus reset has not occurred, the data transfer control system 10 judgeswhether or not a signal DMARQ has been sent from the storage device 100through the bus BUS2 (step S5).

[0109] Specifically, signals such as the DMA transfer request signalDMARQ and a DMARQ acknowledge signal DMACK are defined for the bus BUS2conforming to ATA/ATAPI as described later. If the interface circuit 102of the storage device 100 activates the signal DMARQ and the interfacecircuit 30 of the data transfer control system 10 then activates thesignal DMACK, DMA transfer is started.

[0110] If the signal DMARQ has not been sent from the storage device100, the data transfer control system 10 judges whether or not the busreset has occurred (step S6). If the bus reset has not occurred, thedata transfer control system 10 judges whether or not the signal DMARQhas been sent from the storage device 100. The data transfer controlsystem 10 repeats the judgment in the steps S5 and S6 until the signalDMARQ is sent from the storage device 100.

[0111] If the signal DMARQ is sent from the storage device 100, the datatransfer control system 10 orders start of DMA transfer by activatingthe signal DMACK and the like (step S7). This allows data transferthrough the bus BUS1 (IEEE 1394) and the bus BUS2 (ATA/ATAPI) to beperformed, as indicated by D2 and D3 in FIG. 11.

[0112] Data transfer through the bus BUS1 is implemented by the physicallayer circuit 14, the link layer circuit 20, the SBP-2 circuit 22, andthe like. This allows data stored in the data buffer 4 of the personalcomputer 2 to be written in the packet buffer 40, or data stored in thepacket buffer 40 to be read into the data buffer 4.

[0113] Data transfer through the bus BUS2 is implemented by theinterface circuit 30 and the like. This allows data stored in the packetbuffer 40 to be written in the storage 106 of the storage device 100, ordata stored in the storage 106 to be read into the packet buffer 40.

[0114] The data transfer control system 10 judges whether or not the busreset has occurred (step S8). If the bus reset has not occurred and theDMA transfer is completed (step S9), the data transfer control system 10finishes command processing of the command ORB1 (step S10), and notifiesthe personal computer 2 of the status of the command ORB1 (step S11). Aseries of command processing of the command ORB1 is completed in thismanner.

[0115] If the data transfer control system 10 judges that the bus resethas occurred in the step S2, S4, S6, or S8, reconnect processing inwhich the data transfer control system 10 waits for the initiator toreconnect is performed, as indicated by D4 in FIG. 11 (step S12).

[0116] In SBP-2, an initiator which had logged in to a target before thebus reset can preferentially reconnect with the target for a givenperiod after the bus reset. The initiator can exclusively possess theaccess right to the target (right to use the bus) by performing thereconnect processing after the bus reset.

[0117] If the data transfer control system 10 receives an ORB2 includinga command CMD2 after the reconnect processing (step S13), the datatransfer control system 10 performs command comparison processing forcomparing the contents of the ORB1 (CMD1) before the bus reset with thecontents of the ORB2 after the bus reset, as indicated by D5 in FIG. 11(step S14).

[0118] In this embodiment, a page table present flag P, data size,operation code (code which distinguishes a write command, read command,and the like) and data length in a command block (command set) fieldincluded in the ORB are compared, as shown in FIG. 12. In the case wherethe ORB includes identification information (sequence number, forexample) of the ORB, the identification information may be compared. Inthe case where a page table is not used, values of data descriptors maybe compared. In the case where a page table is used, the number ofsegments may be compared.

[0119] If the above information is compared, whether or not the ORB1before the bus reset is the same as the ORB2 after the bus reset can besecurely judged by using simple processing.

[0120] If the data transfer control system 10 judges that the contentsof the ORB1 are the same as the contents of the ORB2, the data transfercontrol system 10 performs data transfer resume processing of the ORB1(step S15). This enables data transfer to be resumed where the bus resetoccurred as indicated by D6 in FIG. 11. The details of the data transferresume processing are disclosed in Japanese Patent Application Laid-openNo. 2001-177537.

[0121] If the data transfer control system 10 judges that the contentsof the ORB1 differ from the contents of the ORB2 as indicated by E4 inFIG. 13, the data transfer control system 10 judges whether or not thecommand CMD1 included in the ORB1 has been issued to the storage device100 (step S16). If the command CMD1 has not been issued, the datatransfer control system 10 transitions to processing of the ORB2 whichhas been newly sent without performing command abort processing (stepS17). In this embodiment, in the case where the bus reset occurs duringprocessing of the command CMD1, the data transfer control system 10performs abort processing (step S21) if it is judged that the commandCMD1 has been issued (step S16). If it is judged that the command CMD1has not been issued (step S16), the data transfer control system 10transitions to the processing of the ORB2 (step S17) without performingthe abort processing.

[0122] If the command CMD1 has been issued to the storage device 100,the data transfer control system 10 judges whether or not the DMAtransfer has been started (step S18). If the DMA transfer has beenstarted, the data transfer control system 10 transitions to the abortprocessing of the command CMD1, as indicated by E5 in FIG. 13 (stepS21). If the command CMD1 has not been issued, the data transfer controlsystem 10 judges whether or not the DMA transfer request signal DMARQhas been sent from the storage device 100 (step S19). If the signalDMARQ has not been sent from the storage device 100, the data transfercontrol system 10 transitions to the abort processing of the commandCMD1. If the signal DMARQ has been sent from the storage device 100, thedata transfer control system 10 orders start of DMA transfer (step S20),and transitions to the abort processing of the command CMD1. After thedata transfer control system 10 finishes the abort processing of thecommand CMD1, the data transfer control system 10 transitions to theprocessing of the ORB2 (CMD2) (step S17).

[0123]FIG. 10 is a flowchart showing the abort processing of the commandCMD1.

[0124] The data transfer control system 10 judges whether or not the DMAtransfer is active (step S31). For example, if the data transfer controlsystem 10 judges that the DMA transfer has not been started in the stepS 18 in FIG. 9 and that the signal DMARQ has not been sent in the stepS19, the data transfer control system 10 judges that the DMA transfer isnot active in the step S31 in FIG. 10. In this case, the data transfercontrol system 10 aborts the command CMD1 without performing the dummydata transfer control processing in steps S32 to S38. This enables theprocessing in the steps S32 to S38 to be omitted, whereby efficiency ofthe processing can be increased.

[0125] If the data transfer control system 10 judges that the DMAtransfer is active, the data transfer control system 10 judges whetheror not the command CMD1 is either a read command or a write command(step S32).

[0126] If the command CMD1 is a read command, the data transfer controlsystem 10 judges whether or not the DMA transfer based on the commandCMD1 has been completed (step S33). If the DMA transfer has not beencompleted, the data transfer control system 10 performs transferprocessing of dummy data in the steps S33 to S35 between the datatransfer control system 10 and the storage device 100 until the DMAtransfer is completed. If the data transfer control system 10 judgesthat the DMA transfer has been completed, the data transfer controlsystem 10 performs the abort processing of the command CMD1 as indicatedby E7 in FIG. 13 (step S39).

[0127] If the command CMD1 is a write command, the data transfer controlsystem 10 judges whether or not the DMA transfer based on the commandCMD1 has been completed (step S36). If the DMA transfer has not beencompleted, the data transfer control system 10 performs transfer (write)processing of dummy data in the steps S36 to S38 between the datatransfer control system 10 and the storage device 100 until the DMAtransfer is completed. If the data transfer control system 10 judgesthat the DMA transfer has been completed, the data transfer controlsystem 10 performs the abort processing of the command CMD1 (step S39).

[0128] The command abort processing may be implemented by a softwarereset defined in ATA/ATAPI, for example. In more detail, the softwarereset is executed by setting “1” in an SRST bit of a device controlregister included in the interface circuit 102 of the storage device100. The value may be set in the register by allowing the interfacecircuit 30 to access the register of the interface circuit 102 by PIOtransfer using BUS2 signals CS[1:0], DA[2:0], DIOW, DIOR, and the likeas described later.

[0129] In this embodiment, the command CMD1 which has been issued to thestorage device 100 before the bus reset (see step S3 in FIG. 9 and E1 inFIG. 13) is aborted after the DMA transfer (see steps S7 and S20 in FIG.9 and E3 in FIG. 13) started based on the ORB1 (CMD1) is completed (seestep S39 in FIG. 10 and E7 in FIG. 13).

[0130] This allows the command CMD1 to be aborted after the DMA transferbetween the data transfer control system 10 and the storage device 100through the bus BUS2 is completed normally. Therefore, since the storagedevice 100 can normally complete the DMA transfer, occurrence of aproblem in which the storage device 100 hangs can be prevented.Moreover, since the DMA transfer through the bus BUS2 is performed bydummy data transfer until the command CMD1 is aborted, the processing ofthe personal computer 2 is not adversely affected.

[0131] In particular, since the storage device 100 having an ATA(IDE)/ATAPI interface is originally designed as a built-in storagedevice for the personal computer 2, the storage device 100 is notdesigned taking occurrence of the IEEE 1394 bus reset during the DMAtransfer into consideration. Therefore, if the storage device 100 isconnected to the data transfer control system 10 in this embodimenthaving a bridge function between IEEE 1394 and ATA/ATAPI, the storagedevice 100 may hang due to occurrence of an unexpected bus reset.However, according to this embodiment, since the command is abortedafter the DMA transfer is completed, occurrence of hang-up can beprevented.

[0132] 4. Dummy Data Transfer

[0133] The transfer processing of dummy data in the steps S33 to S35 andS36 to S38 in FIG. 10 is described below with reference to FIGS. 14A to14E and 15A to 15E.

[0134]FIGS. 14A to 14E are illustrative of pointer control of the packetbuffer 40 in the case where the personal computer 2 reads data stored inthe storage device 100 (data transfer control system 10 transmits data).

[0135] In FIGS. 14A to 14E, a pointer ATXP1 (first pointer) is a pointerfor writing data transferred from the bus BUS2 (storage device 100,ATA/ATAPI) in the packet buffer 40. The pointer ATXP1 is updated eachtime data transferred from the bus BUS2 is written in the packet buffer40. A pointer LTXP2 (second pointer) is a pointer for reading datatransferred to the bus BUS1 (personal computer 2, IEEE 1394) from thepacket buffer 40. The pointer. LTXP2 is updated each time datatransferred to the bus BUS1 is read from the packet buffer 40. Thesepointers are updated by the pointer management section 39.

[0136] As shown in FIG. 14A, the pointer ATXP1 is updated each time datatransferred from the bus BUS2 is written in the packet buffer 40 by theinterface circuit 30, and a location indicated by the pointer ATXP1 ismoved downward (in the data storage direction). The pointer ATXP1 ismanaged by using a ring buffer. Therefore, when the pointer ATXP1reaches a lower boundary BD2 of the storage region, the pointer ATXP1 isreturned (rings) to an upper boundary BD1 of the storage region, asshown in FIG. 14B.

[0137] If it is judged that ATXP1=LTXP2 (step S34 in FIG. 10), data isstored in the entire storage region of the packet buffer 40, as shown inFIG. 14C. In FIGS. 14A to 14E, a portion indicated by slanted linesdesignates the stored data.

[0138] In this embodiment, the same value is rewritten in the pointerregister of the pointer LTXP2 as shown in FIG. 14D (step S35 in FIG.10). This allows a dummy update on the pointer LTXP2, whereby a resultin which data stored in the entire storage region is read is obtained.The pointer ATXP1 is then updated as shown in FIG. 14E, whereby datatransferred from the bus BUS2 is written in the storage region fromwhich data is read imitatively. The pointer control shown in FIG. 14A to14E is repeated until the DMA transfer is completed (step S33 in FIG.10) so that dummy data is transferred between the data transfer controlsystem 10 and the storage device 100 through the bus BUS2.

[0139] In this embodiment, transfer control of dummy data is implementedby performing a dummy update on the pointer LTXP2 so that the pointerATXP1 (first pointer) which is updated each time data transferred fromthe bus BUS2 is written in the packet buffer 40 does not go ahead of thepointer LTXP2 (second pointer).

[0140]FIGS. 15A to 15E are illustrative of pointer control of the packetbuffer 40 in the case where the personal computer 2 writes data in thestorage device 100 (data transfer control system 10 receives data).

[0141] In FIGS. 15A to 15E, a pointer ARXP3 (third pointer) is a pointerfor reading data transferred to the bus BUS2 from the packet buffer 40.The pointer ARXP3 is updated each time data transferred to the bus BUS2is read from the packet buffer 40. A pointer LRXP4 (fourth pointer) is apointer for writing data transferred from the bus BUS1 in the packetbuffer 40. The pointer LRXP4 is updated each time data transferred fromthe bus BUS1 is written in the packet buffer 40. These pointers areupdated by the pointer management section 39.

[0142] As shown in FIG. 15A, the pointer ARXP3 is updated each time datatransferred to the bus BUS2 is read from the packet buffer 40, and alocation indicated by the pointer ARXP3 is moved downward. The pointerARXP3 is managed by using a ring buffer. Therefore, if the pointer ARXP3reaches the lower boundary BD2, the pointer ARXP3 is returned to theupper boundary BD1.

[0143] If it is judged that ARXP3=LRXP4 (step S37 in FIG. 10), data isread from the entire storage region of the packet buffer 40, as shown inFIG. 15C.

[0144] In this embodiment, the same value is rewritten in the pointerregister of the pointer LRXP4 as shown in FIG. 15D (step S38 in FIG.10). This allows a dummy update on the pointer LRXP4, whereby a resultin which the data is written in the entire storage region is obtained.The pointer ARXP3 is then updated as shown in FIG. 15E, whereby datatransferred to the bus BUS2 is read from the storage region in whichdata is written imitatively. The pointer control shown in FIG. 15A to15E is repeated until the DMA transfer is completed (step S36 in FIG.10) so that dummy data is transferred between the data transfer controlsystem 10 and the storage device 100 through the bus BUS2.

[0145] In this embodiment, the transfer control of dummy data isimplemented by performing a dummy update on the pointer LRXP4 so thatthe pointer ARXP3 (third pointer) which is updated each time datatransferred to the bus BUS2 is read from the packet buffer 40 does notgo ahead of the pointer LRXP4 (fourth pointer).

[0146] In this embodiment, dummy data is transferred imitatively betweenthe data transfer control system 10 and the storage device 100 throughthe bus BUS2 until the DMA transfer is completed, and the command CMD1is aborted after the DMA transfer is completed. The personal computer 2imitatively reads or writes transferred data by performing a dummyupdate on the pointers LTXP2 and LRXP4, as shown in FIGS. 14D and 15D.Therefore, the processing of the personal computer 2 can be preventedfrom being adversely affected if the DMA transfer is continued until thecommand CMD1 is aborted. This enables the ORB2 (CMD2) newly sent fromthe personal computer 2 after the bus reset to be appropriatelyprocessed after the command CMD1 is aborted.

[0147] The method of doing a dummy update on the pointers LTXP2 andLRXP4 is not limited to the method shown in FIGS. 14A to 15D. Itsuffices that the pointers LTXP2 and LRXP4 be controlled so that atleast the pointers ATXP1 and ARXP3 do not go ahead of the pointers LTXP2and LRXP4. The transfer processing of dummy data may be implemented byproviding a hardware circuit exclusive for the dummy data transferinstead of the pointer control shown in FIGS. 14A to 15D.

[0148] 5. ATA/ATAPI Interface Circuit

[0149]FIG. 16 shows a configuration example of the ATA/ATAPI interfacecircuit 30. The interface circuit 30 does not necessarily include allthe circuit blocks shown in FIG. 16. Some of the circuit blocks may beomitted.

[0150] A FIFO 31 is a buffer for adjusting (buffering) the difference indata transfer rate. A DMA controller 32 is a circuit which controls(REQ/ACK control) the FIFO 31 and an interface core circuit 34.

[0151] The interface core circuit 34 is a circuit which controls DMAtransfer and the like. A counter 35 included in the interface corecircuit 34 is an ATA (IDE)/ATAPI reset counter. A UDMA circuit 36included in the interface core circuit 34 is a circuit for controllingATA/ATAPI UltraDMA transfer. The UDMA circuit 36 includes a UltraDMAFIFO 37 and a UltraDMA CRC calculation circuit 38.

[0152] A register 33 is a register for controlling initiation of DMAtransfer and the like. The register 33 is accessible by the firmware 50(CPU 42).

[0153] A signal CS[1:0] is a chip select signal used to access each ATAregister. A signal DA[2:0] is an address signal for accessing data or adata port.

[0154] The signals DMARQ and DMACK are signals used for DMA transfer.The storage device 100 (device) activates (asserts) the signal DMARQwhen preparations for data transfer are completed, and the data transfercontrol system 10 (host) activates the signal DMACK when initiating theDMA transfer in response to the signal DMARQ.

[0155] A signal DIOW (STOP) is a write signal used to write data in aregister or a data port. The signal DIOW functions as a STOP signalduring UrtraDMA transfer. A signal DIOR (HDMARDY, HSTROBE) is a readsignal used to read data from a register or a data port. The signal DIORfunctions as an HDMARDY/HSTROBE signal during UrtraDMA transfer.

[0156] A signal IORDY (DDMARDY, DSTROBE) is used as a wait signal or thelike when the storage device 100 does not complete preparations for datatransfer. The signal IORDY functions as a DDMARDY/DSTROBE signal duringUrtraDMA transfer.

[0157]FIGS. 17A to 19B show signal waveform examples of the above ATAsignals. In FIGS. 17A to 19B, “#” designates that the signal is anegative logic signal (active at L level).

[0158]FIGS. 17A and 17B are signal waveform examples during PIO(Parallel I/O) reading and PIO writing. The ATA status register is readby the PIO reading shown in FIG. 17A. The control register is written bythe PIO writing shown in FIG. 17B. For example, a software reset foraborting a command issued to the storage device 100 is generated bysetting “1” in the SRST bit of the register of the interface circuit 102by the PIO writing shown in FIG. 17B.

[0159]FIGS. 18A and 18B are signal waveform examples during DMA readingand DMA writing. The storage device 100 (interface circuit 102)activates the signal DMARQ (H level) when preparations for data transferare completed. The data transfer control system 10 (interface circuit30) activates the signal DMACK (L level) in response to the signal DMARQto initiate DMA transfer. The DMA transfer of data DD[15:0] is performedby using the signal DIOR (during reading) or DIOW (during writing).

[0160]FIGS. 19A and 19B are signal waveform examples during UltraDMAreading and UltraDMA writing. The storage device 100 activates thesignal DMARQ when preparations for data transfer are completed. The datatransfer control system 10 activates the signal DMACK in response to thesignal DMARQ to initiate DMA transfer. The UltraDMA transfer of dataDD[15:0] is performed by using the signals DIOW, DIOR, and IORDY.

[0161] Note that the present invention is not limited to theabove-described embodiments, and various modifications can be madewithin the scope of the invention.

[0162] For example, in part of this specification, terms such as IEEE1394, ATA/ATAPI, SBP-2, IPover1394, ORB, a personal computer/storagedevice, a hard disk drive/optical disk drive, a storage device and CPUare replaced by terms in a broader sense such as a first interfacestandard, a second interface standard, a first higher level protocol ofthe first interface standard, a second higher level protocol of thefirst interface standard, a command packet, an electronic instrument, astorage device, a device and a processor, but these terms may bereplaced also in another part of the specification.

[0163] Part of requirements of any claim of the present invention couldbe omitted from a dependent claim which depends on that claim. Moreover,part of requirements of any independent claim of the present inventioncould be made to depend on any other independent claim.

[0164] The configuration of the data transfer control system and theelectronic instrument of the present invention is not limited to theconfiguration shown in FIG. 8, and various modifications are possible.For example, part of the circuit blocks and the functional blocks shownin FIGS. 9 and 18 may be omitted, or the connection between the blocksmay be modified. The second bus (BUS2) may be connected to a deviceother than the storage device. The connection of the physical layercircuit, the link layer circuit, and the packet buffer is not limited tothe connection shown in FIG. 8.

[0165] Although the embodiments illustrate the case where the functionsof the command processing section, command abort section, commandcomparison section, transfer resume section, and the like areimplemented by the firmware (program), part or all of these functionsmay be implemented by hardware.

[0166] The present invention is particularly useful for the bus reset inIEEE 1394. However, the present invention may be applied to anotherreset which clears at least the node topology information. The presentinvention may be applied to command abort processing performed in thetime other than the bus reset.

[0167] The present invention may be applied to various types ofelectronic appliances (such as hard disk drives, optical disk drives,magneto-optical disc drives, PDAs, expansion devices, audio devices,digital video cameras, portable telephones, printers, scanners, TVs,VCRs, telephones, display devices, projectors, personal computers, orelectronic notebooks).

[0168] The embodiments of the present invention describe the case wherethe present invention is applied to the data transfer conforming to theIEEE 1394, SBP-2, and ATA/ATAPI standards. However, the presentinvention may be applied to data transfer conforming to standards basedon concepts similar to those of the IEEE 1394 (P1394a), SBP-2 (SBP), andATA/ATAPI, or on standards developed from the IEEE 1394, SBP-2, andATA/ATAPI.

[0169] The specification discloses the following matters about theconfiguration of the embodiments described above.

[0170] According to one embodiment of the present invention, there isprovided a data transfer control system for data transfer through a bus,comprising:

[0171] a command processing section which receives a command packettransferred through a first bus, issues a command indicated by thecommand packet to a device connected to a second bus, and orders startof a direct memory access (DMA) transfer through the second bus; and

[0172] a command abort section which aborts the command issued to thedevice connected to the second bus based on the command packet after thecompletion of the DMA transfer started based on the command packet.

[0173] In this data transfer control system, the command indicated bythe command packet transferred through the first bus is issued to thedevice connected to the second bus, and the DMA transfer is started. Thecommand issued to the device connected to the second bus is aborted (orcancelled) after the completion of the DMA transfer. This preventsoccurrence of a problem such as a hang-up of the device connected to thesecond bus when the DMA transfer is terminated abnormally, whereby thecommand issued to the device can be aborted appropriately. Note that thefirst bus may be a bus which transfers data conforming to a firstinterface standard and the second bus may be a bus which transfers dataconforming to a second interface standard, for example.

[0174] The data transfer control system may further comprise a commandcomparison section which compares contents of a first command packettransferred through the first bus before a bus reset with contents, of asecond command packet transferred through the first bus after the busreset, when the bus reset that clears node topology information hasoccurred during the processing of the first command packet, wherein thecommand abort section may abort a command which has been issued to thedevice connected to the second bus based on the first command packetafter completion of a DMA transfer which has been started based on thefirst command packet, when the contents of the first command packet aredetermined to be different from the contents of the second commandpacket.

[0175] If the contents of the first and second command packets aredetermined to be the same, the data transfer can be resumed from thepoint of the bus reset occurrence.

[0176] In this data transfer control system, when a bus reset thatclears node topology information occurs during processing of a firstcommand packet,

[0177] in a case where a command of the first command packet has beenissued to the device connected to the second bus, the command of thefirst command packet may be aborted, and

[0178] in a case where the command of the first command packet has notbeen issued to the device connected to the second bus, processing of asecond command packet may start without aborting the command of thefirst command packet.

[0179] In this data transfer control system, the command abort sectionmay control dummy data transfer to or from the device connected to thesecond bus until the completion of the DMA transfer.

[0180] In this case, dummy data transfer control may be implemented byperforming a dummy update on a pointer of a packet buffer whichtemporarily stores transferred data, or by providing hardware for dummydata transfer. The dummy data may be data which is transferred throughthe second bus, but is not transferred through the first bus, forexample.

[0181] In this data transfer control system, the command abort sectionmay abort a command without controlling dummy data transfer when any DMAtransfer is not being performed in determination of whether or not thecommand is to be aborted.

[0182] This enables the processing of dummy data transfer control to beomitted, whereby processing efficiency can be improved.

[0183] The data transfer control system may further comprise:

[0184] a pointer management section which manages pointers for a packetbuffer which is a ring buffer and temporarily stores transferred data,the pointer management section updating a first pointer each time whendata transferred from the second bus is written in the packet buffer,and also updating a second pointer each time when data to be transferredto the first bus is read from the packet buffer,

[0185] wherein the command abort section may control dummy data transferby performing a dummy update on the second pointer so that the firstpointer does not go ahead of the second pointer.

[0186] The data transfer control system may further comprise:

[0187] a pointer management section which manages pointers for a packetbuffer which is a ring buffer and temporarily stores transferred data,the pointer management section updating a third pointer each time whendata to be transferred to the second bus is read from the packet buffer,and also updating a fourth pointer each time when data transferred fromthe first bus is written in the packet buffer,

[0188] wherein the command abort section controls dummy data transfer byperforming a dummy update on the fourth pointer so that the thirdpointer does not go ahead of the fourth pointer.

[0189] In this data transfer control system, the first bus may transferdata conforming to the IEEE 1394 standard, and the second bus maytransfer data conforming to the Advanced Technology Attachment/AdvancedTechnology Attachment Packet Interface (ATA/ATAPI) standard.

[0190] According to another embodiment of the present invention, thereis provided an electronic instrument comprising any of the above datatransfer control systems and the device connected to the second bus.

[0191] According to further embodiment of the present invention, thereis provided a program causing a data transfer control system to functionas:

[0192] a command processing section which receives a command packettransferred through a first bus, issues a command indicated by thecommand packet to a device connected to a second bus, and orders thestart of a direct memory access (DMA) transfer through the second bus;and

[0193] a command abort section which aborts the command issued to thedevice connected to the second bus based on the command packet after thecompletion of the DMA transfer started based on the command packet.

[0194] According to still another embodiment of the present invention,there is provided a data transfer control method for data transferthrough a bus, the method comprising:

[0195] issuing a command indicated by a command packet transferredthrough a first bus, to a device connected to a second bus, and orderingstart of a direct memory access (DMA) transfer through the second bus;and

[0196] aborting the command issued to the device connected to the secondbus based on the command packet after the completion of the DMA transferstarted based on the command packet.

What is claimed is:
 1. A data transfer control system for data transferthrough a bus, comprising: a command processing section which receives acommand packet transferred through a first bus, issues a commandindicated by the command packet to a device connected to a second bus,and orders start of a direct memory access (DMA) transfer through thesecond bus; and a command abort section which aborts the command issuedto the device connected to the second bus based on the command packetafter the completion of the DMA transfer started based on the commandpacket.
 2. The data transfer control system as defined in claim 1,further comprising: a command comparison section which compares contentsof a first command packet transferred through the first bus before a busreset with contents of a second command packet transferred through thefirst bus after the bus reset, when the bus reset that clears nodetopology information has occurred during the processing of the firstcommand packet, wherein the command abort section aborts a command whichhas been issued to the device connected to the second bus based on thefirst command packet after completion of a DMA transfer which has beenstarted based on the first command packet, when the contents of thefirst command packet are determined to be different from the contents ofthe second command packet.
 3. The data transfer control system asdefined in claim 1, wherein: when a bus reset that clears node topologyinformation occurs during processing of a first command packet, in acase where a command of the first command packet has been issued to thedevice connected to the second bus, the command of the first commandpacket is aborted, and in a case where the command of the first commandpacket has not been issued to the device connected to the second bus,processing of a second command packet starts without aborting thecommand of the first command packet.
 4. The data transfer control systemas defined in claim 1, wherein the command abort section controls dummydata transfer to or from the device connected to the second bus untilthe completion of the DMA transfer.
 5. The data transfer control systemas defined in claim 4, wherein the command abort section aborts acommand without controlling dummy data transfer when any DMA transfer isnot being performed in determination of whether or not the command is tobe aborted.
 6. The data transfer control system as defined in claim 4,further comprising: a pointer management section which manages pointersfor a packet buffer which is a ring buffer and temporarily storestransferred data, the pointer management section updating a firstpointer each time when data transferred from the second bus is writtenin the packet buffer, and also updating a second pointer each time whendata to be transferred to the first bus is read from the packet buffer,wherein the command abort section controls dummy data transfer byperforming a dummy update on the second pointer so that the firstpointer does not go ahead of the second pointer.
 7. The data transfercontrol system as defined in claim 4, further comprising: a pointermanagement section which manages pointers for a packet buffer which is aring buffer and temporarily stores transferred data, the pointermanagement section updating a third pointer each time when data to betransferred to the second bus is read from the packet buffer, and alsoupdating a fourth pointer each time when data transferred from the firstbus is written in the packet buffer, wherein the command abort sectioncontrols dummy data transfer by performing a dummy update on the fourthpointer so that the third pointer does not go ahead of the fourthpointer.
 8. The data transfer control system as defined in claim 1,wherein the first bus transfers data conforming to the IEEE 1394standard, and the second bus transfers data conforming to the AdvancedTechnology Attachment/Advanced Technology Attachment Packet Interface(ATA/ATAPI) standard.
 9. An electronic instrument comprising: the datatransfer control system as defined in claim 1; and the device connectedto the second bus.
 10. A program causing a data transfer control systemto function as: a command processing section which receives a commandpacket transferred through a first bus, issues a command indicated bythe command packet to a device connected to a second bus, and orders thestart of a direct memory access (DMA) transfer through the second bus;and a command abort section which aborts the command issued to thedevice connected to the second bus based on the command packet after thecompletion of the DMA transfer started based on the command packet. 11.The program as defined in claim 10 causing the data transfer controlsystem to further function as: a command comparison section whichcompares contents of a first command packet transferred through thefirst bus before a bus reset with contents of a second command packettransferred through the first bus after the bus reset, when the busreset that clears node topology information has occurred during theprocessing of the first command packet, wherein the command abortsection aborts a command which has been issued to the device connectedto the second bus based on the first command packet after completion ofa DMA transfer which has been started based on the first command packet,when the contents of the first command packet are determined to bedifferent from the contents of the second command packet.
 12. Theprogram as defined in claim 10, wherein the command abort sectioncontrols dummy data transfer to or from the data transfer control systemand the device connected to the second bus until the completion of theDMA transfer.
 13. A data transfer control method for data transferthrough a bus, the method comprising: issuing a command indicated by acommand packet transferred through a first bus, to a device connected toa second bus, and ordering start of a direct memory access (DMA)transfer through the second bus; and aborting the command issued to thedevice connected to the second bus based on the command packet after thecompletion of the DMA transfer started based on the command packet. 14.The data transfer control method as defined in claim 13, furthercomprising: comparing contents of a first command packet transferredthrough the first bus before a bus reset with contents of a secondcommand packet transferred through the first bus after the bus reset,when the bus reset that clears node topology information has occurredduring the processing of the first command packet; and aborting acommand which has been issued to the device connected to the second busbased on the first command packet after completion of a DMA transferwhich has been started based on the first command packet, when thecontents of the first command packet are determined to be different fromthe contents of the second command packet.
 15. The data transfer controlmethod as defined in claim 13, when a bus reset that clears nodetopology information occurs during processing of a first command packet,further comprising: aborting a command of the first command packet, in acase where the command of the first command packet has been issued tothe device connected to the second bus; and starting processing of asecond command packet without aborting the command of the first commandpacket, in a case where the command of the first command packet has notbeen issued to the device connected to the second bus,.
 16. The datatransfer control method as defined in claim 13, further comprising:controlling dummy data transfer to or from the device connected to thesecond bus until the completion of the DMA transfer.
 17. The datatransfer control method as defined in claim 16, further comprising:aborting a command without controlling dummy data transfer when any DMAtransfer is not being performed in determination of whether or not thecommand is to be aborted.
 18. The data transfer control method asdefined in claim 16, further comprising: managing pointers for a packetbuffer which is a ring buffer and temporarily stores transferred data, afirst pointer being updated each time when data transferred from thesecond bus is written in the packet buffer, and a second pointer beingupdated each time when data to be transferred to the first bus is readfrom the packet buffer; and controlling dummy data transfer byperforming a dummy update on the second pointer so that the firstpointer does not go ahead of the second pointer.
 19. The data transfercontrol method as defined in claim 16, further comprising: managingpointers for a packet buffer which is a ring buffer and temporarilystores transferred data, a third pointer being updated each time whendata to be transferred to the second bus is read from the packet buffer,and a fourth pointer being updated each time when data transferred fromthe first bus is written in the packet buffer; and controlling dummydata transfer by performing a dummy update on the fourth pointer so thatthe third pointer does not go ahead of the fourth pointer.
 20. The datatransfer control method as defined in claim 13, wherein the first bustransfers data conforming to the IEEE 1394 standard and the second bustransfers data conforming to the Advanced Technology Attachment/AdvancedTechnology Attachment Packet Interface (ATA/ATAPI) standard.